1. Field of the Invention
The present invention relates to semiconductor device fabrication methods and, in particular, to methods for the formation of polysilicon layers of controlled, small silicon grain size.
2. Description of the Related Art
Polysilicon layers are frequently employed as the gate electrode in metal-oxide-semiconductor (MOS) devices. See S. Wolf, Silicon Processing for the VLSI Era, Volume 2--Process Integration, Lattice Press, 318-319 (1990) and U.S. Pat. Nos. 5,147,813 and 5,229,631 to Been-Jon Woo. As the width of such a polysilicon gate electrode is reduced to 0.18 .mu.m and beyond, and its height is reduced to 1500 angstroms and below, the morphology (e.g., silicon grain structure) of the polysilicon layer becomes increasingly important in determining various characteristics of the MOS device. Characteristics that can be affected by the silicon grain structure of a polysilicon layer include (i) depletion of dopant in the polysilicon gate electrode due to channeling during ion implantation, as well as dopant diffusion effects in the polysilicon gate electrode; and (ii) boron penetration through the polysilicon gate electrode during ion implantation and a consequent reduction in the integrity of a gate silicon dioxide layer that underlies the polysilicon gate electrode. Furthermore, the relatively high surface roughness of polysilicon layers can be detrimental to the photolithographic patterning processes used in semiconductor device fabrication.
The average surface roughness of as-deposited amorphous silicon layers is known to be lower than the average surface roughness of as-deposited polysilicon layers. In addition, the amorphous nature of these silicon layers reduces channeling during ion implantation. As-deposited amorphous silicon layers are, however, typically subjected to numerous thermal cycles during subsequent semiconductor fabrication processes. These thermal cycles can convert the as-deposited amorphous silicon layer into a polysilicon layer of uncontrolled and relatively large silicon grain size. The growth and morphology of polysilicon and amorphous silicon layers have, therefore, been the subject of extensive investigation. See, for example, M. T. Duffy, et al., LPCVD Polycrystalline Silicon. Growth and Physical Properties of Diffusion-Doped, Ion-Implanted, and Undoped Films, RCA Review, Vol. 44, 313-325 (1983); G. Harbeke et al., Growth and Physical Properties of LPCVD Polycrystalline Silicon Films, J. Electrochem. Soc., Vol. 131, No. 3, 675-682 (1984); J. Morgiel et al., In Situ HREM Observations of Crystallization in LPCVD Amorphous Silicon, Mat. Res. Soc. Symp. Proc. Vol. 182, 191-194 (1990); O. S. Panwar et al., Comparative Study of Large Grains and High Performance TFTs in Low Temperature Crystallized LPCVD and APCVD Amorphous Silicon Films, Thin Solid Films 237, 255-267 (1994); and J. Lutzen et al., Structural Characterization of Ultrathin Nanocrystalline Silicon Films Formed by Annealing Amorphous Silicon, J. Vac. Sci. Technology B 16(5), 2802-2805 (1998) for further discussions of the subject.
The use of recrystallized amorphous silicon layers as polysilicon gate electrodes has been reported in the literature. See Shimizu et al., Gate Electrode Engineering by Control of Grain Growth for High Performance and High Reliable 0.18 .mu.m Dual Gate CMOS, 1997 Symposium on VLSI Technology, Digest of Technical Papers, 107-108 (1997). However, the relatively high temperatures and long time periods that were employed for recrystallization of the amorphous silicon layers (for example, 850.degree. C. for 20 minutes and 610.degree. C. for 3 hours) can lead to unwanted dopant redistribution in an underlying semiconductor substrate and the formation of undesirably large silicon grains in the resulting polysilicon layer.
Still needed in the field, therefore, is a process for controlling the grain size of polysilicon layers during semiconductor device manufacturing that is compatible with conventional semiconductor device fabrication techniques.